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Chrontel
CH7021A
Brief Datasheet
CH7021A SDTV / HDTV Encoder
Features
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General Description
The CH7021A is a Display Controller device which accepts a digital graphics input signal, and encodes and transmits data through analog SDTV ports (analog composite, s-video, RGB or YPrPb) or an analog HDTV port (YPrPb). The device is able to encode the video signals and generate synchronization signals for NTSC, PAL and SECAM SDTV standards, as well as analog HDTV interface standards and graphics standards up to UXGA. The device accepts one channel of RGB data over three pairs of serial data ports. The TV-Out processor will perform scaling to convert VGA frames to supported SDTV and HDTV output standards. Adaptive de-flicker filter provides superior text display. Large numbers of input graphics resolutions are supported up to 1600 by 1200 with full vertical and horizontal overscan compensation in all output standards. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. In addition to scaling modes, bypass modes are included which perform color space conversion to SDTV or HDTV standards and generate and insert SDTV or HDTV sync signals, or output VGA style analog RGB for use as a CRT DAC. Different analog video connectors are supported including composite, s-video, YPrPb, SCART, D-connector and VGA connector. Content protection support is provided for MacrovisionTM in SDTV and EDTV modes. CGMS-A is also provided up to 1080i resolution.
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VGA to SDTV/EDTV/HDTV conversion supporting graphics resolutions up to 1600x1200 HDTV support for 480p, 576p, 720p, 1080i and 1080p Support for NTSC, PAL, SECAM color modulation. MacrovisionTM 7.1.L1 copy protection support for SDTV MacrovisionTM copy protection support for progressive scan TV (480p, 576p) CGMS-A support for SDTV and HDTV High-speed SDVO (1G~2Gbps) AC-coupled serial differential RGB inputs Flexible TrueScaleTM rendering engine supports overscan compensation in all SDTV/EDTV and HDTV output resolutions Text enhancement filter in scan conversion Adaptive de-flicker filter with up to 7 lines of filtering in scan conversion Contrast/Brightness/Sharpness control for TV output. Hue/Saturation Control for TV output. Support for SCART connector Support for HDTV D-Connector Outputs CVBS, S-Video, RGB and YPbPr Support for VGA RGB bypass TV / Monitor connection detect Programmable power management Four 10-bit video DAC outputs Three sets of DAC outputs supporting SDTV / HDTV / CRT RGB connectors Fully programmable through serial port Configuration through Intel(R) SDVO OpCode Complete Windows driver support Offered in a 64-pin LQFP package
Patent number 5,781,241 Patent number 5,914,753 Intel Proprietary.
209-0000-032
Rev. 1.0,
3/21/2005
1
CHRONTEL
XI/FIN,XO TVCLK(+,-)
2
CH7021A
PLL Serial Port Control AS SPC SPD RESET*
VSYNC CHSYNC DL1,DL2,DL3
Control
3 CVBS, S-Video, RGB, YPbPr DAC 3
SC_DDC SD_DDC SC_PROM SD_PROM
SDVO_Clk(+,-)
2
Clock Driver
Color Space Conversion
Scaling Scan Conv Flicker Filt
NTSC/PAL/ SECAM Encoder
CVBS R C Pr G Y Y B CVBS Pb ISET
DAC 2 MUX
10bit-8bit decoder SDVO_R(+,-) SDVO_G(+,-) SDVO_B(+,-)
HDTV Encoder
YPbPr
DAC 1
DAC 0 6
Data Latch, Serial to Parallel
RGB, Bypass
Four 10-bit DAC's
Figure 1: Functional Block Diagram
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CHRONTEL
1.0 Pin-Out
1.1 Package Diagram
CH7021A
SDVO_CLK+ AGND SDVO_B-
SDVO_CLK-
AVDD SDVO_GSDVO_G+
SDVO_RSDVO_R+
SDVO_B+
AGND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
T1 SD_DDC SC_DDC SD_PROM SC_PROM DVDD RESET* AS DGND DGND SPD SPC DVDD BSCAN T3 VDAC2
AGND
AVDD
AVDD
RPLL
T2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Chrontel CH7021
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DL3 DL2 DL1 AGND_TVPLL2 TVCLKTVCLK+ AVDD_TVPLL2 AVDD_TVPLL1 XO XI/FIN AGND_TVPLL1 DGND VSYNC DVDD CHSYNC V5V
DACA[3]
VDAC1 DACA[2]
DACB[2]
DACA[1]
DACB[1]
DACC[2]
DACC[1]
DACA[0] DACB[0]
DACC[0]
GDAC1
GDAC2
Figure 2: 64-Pin LQFP Package
209-0000-032
Rev. 1.0,
3/21/2005
GDAC0
VDAC0
ISET
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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CHRONTEL
1.2 Pin Description
Table 1: Pin Description Pin # 1,51 2 Type Out In/Out Symbol T1,T2 SD_DDC Description Test These pins are reserved for factory test.
CH7021A
3 4
In/Out In/Out
SC_DDC SD_PROM
5 7 8 11
Out In In In/Out
SC_PROM RESET* AS SPD
Routed Serial Port Data Output to DDC This pin functions as the bi-directional data pin of the serial port to DDC receiver. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. Routed Serial Port Clock Output to DDC This pin functions as the clock bus of the serial port to DDC receiver. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. Routed Data Output to PROM This pin functions as the bi-directional data pin of the serial port for PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. Routed Clock Output to PROM This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused.
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. This pin is 3.3V compliant.
Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external 4k - 9 k pull up resistor to 2.5V.
12 14
In/Out In
SPC BSCAN
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with inputs from 0 to 2.5V. This pin requires an external 4k - 9k pull up resistor to 2.5V.
15
In
T3
BSCAN (internal pull low) This pin should be left open or pulled low with a 10k resistor in the application. This pin enables the boundary scan for in-circuit testing. Voltage level is 0 to DVDD. This pin should be pulled low during normal operation. Test (internal pull-down) This pin should be left open or pulled low with a 10k resistor in the application.
DAC Output A Video Digital-to-Analog outputs. Refer to section Error! Reference source not found. for information regarding support for Composite Video, S-Video, SCART, YPrPb and RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load.
18,20,24,28 Out
DACA[3:0]
21,25,29
Out
DACB[2:0]
DAC Output B
Video Digital-to-Analog outputs. Refer to section Error! Reference source not found. for information regarding supports for Composite Video, S-Video, SCART, YPrPb and RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load.
Intel Proprietary.
4
209-0000-032
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CHRONTEL
Table 1: Pin Description (contd.) Pin # 22,26,30 Type Out Symbol
DACC[2:0]
CH7021A
Description DAC Output C
Video Digital-to-Analog outputs. Refer to section Error! Reference source not found. for information regarding supports for Composite Video, S-Video, SCART, YPrPb and RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load.
32 34 36 39
In Out Out In
ISET CHSYNC VSYNC XI/FIN
Current Set Resistor Input
This pin sets the DAC current. A 1.2Kohm resistor should be connected between this pin and DAC ground (pin 31) using short and wide traces.
Composite / Horizontal Sync Output
A buffered version of VGA composite sync as well as horizontal sync can be acquired from this pin.
VSYNC
A buffered version of VGA vertical sync can be acquired from this pin.
40
Out
XO
43,44
Out
TVCLK+/-
Crystal Input / External Reference Input A parallel resonant 27MHz crystal (20 ppm) should be attached between this pin and XO. However, an external CMOS clock can drive the XI/FIN input. Crystal Output A parallel resonance 27MHz crystal (20 ppm) should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to the XI/FIN input, XO should be left open. Pixel Clock Output
When the chip is operating as a TV encoder in master clock mode, this pair outputs a differential clock to the VGA controller. The VGA controller uses this as a reference frequency to generate SDVO_CLK+/- to the chip. The clock frequency is between 100MHz ~ 200MHz. This clock pair will run at an integer multiple of the desired input pixel rate. Refer to section Error! Reference source not found. for details. D-Connector Line 1 Video format identification line for HDTV D-Connector. See section Error! Reference source not found.. D-Connector Line 2 Video format identification line for HDTV D-Connector. See section Error! Reference source not found.. D-Connector Line 3 Video format identification line for HDTV D-Connector. See section Error! Reference source not found..
46 47 48 50
Out Out Out In
DL1 DL2 DL3 RPLL
53,54,56,57 In 59,60 62,63 In
SDVO_R+/-, These pins accept 3 AC-coupled differential pair of RGB inputs from a digital video SDVO_G+/-, port of a graphics controller. SDVO_B+/SDVO_CLK+/- Differential Clock Input associated with SDVO Data channel (SDVO_R+/-,
PLL Resistor Input External resistor 10Kohm should be connected between this pin and pin 49. SDVO Data Channel Inputs
SDVO_G+/-, SDVO_B+/-) The range of this clock pair is 100~200MHz. For specified pixel rates in specified modes this clock pair will run at an integer multiple of the pixel rate. Refer to section Error! Reference source not found. for details.
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Rev. 1.0,
3/21/2005
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CHRONTEL
CH7021A
Table 1: Pin Description (contd.) Pin # 6,13,35 9,10,37 16 17 19 23 27 31 41 38 42 45 52,58,64 49,55,61 33 Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Symbol DVDD DGND VDAC2 GDAC2 VDAC1 GDAC1 VDAC0 GDAC0 AVDD_TVPLL1 AGND_TVPLL1 AVDD_TVPLL2 AGND_TVPLL2 AVDD AGND V5V Description Digital Supply Voltage (2.5V) Digital Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground TV PLL1 Supply Voltage (2.5V) TV PLL1 Ground TV PLL2 Supply Voltage (2.5V) TV PLL2 Ground Analog Supply Voltage (2.5V) Analog Ground D-Connector Supply Voltage (5V)
6
209-0000-032
Rev. 1.0,
3/21/2005
CHRONTEL
2.0 Package Dimensions
TOP VIEW
A
CH7021A
BOTTOM VIEW
B K 48 49 33 32
B
A
K
64 1 16
17
C
D
EXPOSED PAD
F
E
.008"
I J H
G
Figure 3: 64 Pin LQFP (Exposed Pad) Package Table of Dimensions No. of Leads 64 (10 X 10 mm) MIN Millimeters MAX
A 12 B 10 C 0.50 D 0.17 0.27 E 1.35 1.45
SYMBOL
F 0.05 0.15 G 1.00 H 0.45 0.75 I 0.09 0.20 J 0 7 K 5.85 7
Notes: 1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
209-0000-032
Rev. 1.0,
3/21/2005
7
CHRONTEL
Disclaimer
CH7021A
This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number CH7021A-TE CH7021A-TE-TR CH7021A-TEF CH7021A-TEFTR Package Type LQFP with exposed pad LQFP with exposed pad in Tape & Reel Lead Free LQFP with exposed pad Lead Free LQFP with exposed pad in Tape & Reel Number of Pins 64 64 64 64 Voltage Supply 2.5V & 3.3V 2.5V & 3.3V 2.5V & 3.3V 2.5V & 3.3V
Chrontel
2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)2005 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.
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209-0000-032
Rev. 1.0,
3/21/2005

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